Closed loop sub-carrier synchronization system

ABSTRACT

A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received sub-carrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This patent application is a continuation of U.S. patent applicationSer. No. 10/794,601, filed Mar. 5, 2004, issued as U.S. Pat. No.7,372,929, which makes reference to, claims priority to and claims thebenefit of U.S. Provisional Application No. 60/452,229, filed Mar. 5,2003. The above-referenced United States applications are herebyincorporated herein by reference in their entirety.

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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SEQUENCE LISTING

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MICROFICHE/COPYRIGHT REFERENCE

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BACKGROUND OF THE INVENTION

Communication systems may utilize sub-carriers to modulate communicatedinformation. Digital communication systems may sample signals prior toprocessing the information modulated by the sub-carrier. Digitalcommunication systems may perform a vast array of operations on receivedsignals, including comparing and analyzing signals received at differentinstances in time.

For example, in the video communication field, a video signal processingsystem may analyze information in adjacent field or frame lines todetermine various characteristics of the incoming video information. Thevideo signal processing system may also compare corresponding field orframe lines in adjacent video fields or frames to determine variouscharacteristics of the incoming video information. The video signalprocessing system may, for example, perform two-dimensional orthree-dimensional comb filtering on an incoming video signal todetermine chrominance and luminance information contained in the videosignal. Such filtering may involve, for example, utilizing a pluralityof field lines in a particular video field (i.e., two-dimensional combfiltering), and may additionally involve, for example, utilizingcorresponding field lines in temporally separate video fields or frames(i.e., three-dimensional comb filtering).

It is often desirable, when processing signals received at differenttimes, over different channels or over, for example, different media, toalign the signals being processed. This alignment may generally be atemporal alignment, but may also be viewed, for example, as a phasealignment. For example, when processing lines from two video fields inan interlaced video stream, it may be desirable to align the phases ofthe respective sub-carriers of the lines from the two video fields. Suchsignals may also have been digitally sampled, in which case, it may bedesirable to align the corresponding digital data samples to sample andsub-sample accuracy.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with the present invention as set forth inthe remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A system and method are provided for synchronizing signals according totheir sub-carriers in a signal processing system. Various aspects of thepresent invention may receive a current sampled signal that includesinformation modulated using a sub-carrier. Various aspects may generatea synchronization signal based on the current sampled signal orpreviously received sampled signals. For example, various aspects may,in a video context, generate horizontal sync, vertical sync, and fieldidentity signals. Various aspects may generate a cropped version of thecurrent sampled signal. For example, various aspects may delete samplesfrom the current sampled signal that are not necessary. For example, ina video context, various aspects may delete samples from the currentsampled signal that correspond generally to information that does notcorrespond to active video information. Various aspects may then storethe cropped version of the current sampled signal in memory. Variousaspects may also store in memory an indication of which samples werecropped to form the cropped version of the current sampled signal.

Various aspects of the present invention may retrieve a cropped storedsampled signal from memory that corresponds to the current sampledsignal. Various aspects may generate a restored sampled signal based onthe cropped stored sampled signal by, for example, adding samples to thecropped stored sampled signal. Various aspects may, for example, readfrom memory an indication of which samples were cropped from theoriginal sampled signal to form the cropped stored sampled signal.Various aspects may then add samples to the cropped stored sampledsignal according to the indication of removed samples.

Various aspects of the present invention may output the restored sampledsignal and the current sampled signal coarsely synchronized. Variousaspects may, for example, utilize the synchronization signal to effectsuch coarse synchronization. Various aspects of the present inventionmay analyze the phase difference between the sub-carrier of the outputcurrent sampled signal and the sub-carrier of the output restoredsampled signal and generate an indication of phase difference. Variousaspects may then adjust the timing or phase of the output signals inresponse to the indication of phase difference. Various aspects of thepresent invention may continually monitor the phase difference betweenthe sub-carriers of the output restored sampled signal and the outputcurrent sampled signal to determine if synchronization is lost.

These and other advantages, aspects and novel features of the presentinvention, as well as details of illustrative aspects thereof, will bemore fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a diagram illustrating exemplary video frame interval timing.

FIG. 2 is a diagram illustrating aspects of a system for synchronizingvideo signals according to their sub-carriers in accordance with variousaspects of the present invention.

FIG. 3 is a diagram illustrating aspects of stored video signal samplesand additional information in accordance with various aspects of thepresent invention.

FIG. 4 is a diagram illustrating aspects of synchronization control inaccordance with various aspects of the present invention.

FIG. 5 is a diagram illustrating aspects of a method for synchronizingvideo signals according to their sub-carriers in accordance with variousaspects of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a diagram 100 illustrating exemplary video frame intervaltiming. The illustrated example is a diagram for a typical interlacedvideo stream. The exemplary video stream includes an interlacedstructure of top and bottom video fields. Each field, in turn, mayinclude a plurality of video lines. For the following discussion, theBottom Field N will be considered to be the bottom field following TopField N. This is a convention for the following discussion and should byno means limit the scope of various aspects of the present invention.For example and without limitation, a Top Field N and a Bottom Field Nmay be paired under certain conditions and the Bottom Field N and TopField N+1 may be paired under certain other conditions.

Top Field N may include a plurality of video lines, and Bottom Field Nmay include a plurality of video lines interlaced with the video linesof Top Field N. Top Field N+1 may have a plurality of video lines thatcorrespond spatially, but not temporally, with the plurality of videolines in Top Field N. Similarly, Bottom Field N+1 may, for example, havea plurality of video lines that correspond spatially, but nottemporally, with the plurality of video lines in Bottom Field N.

A video signal processing system may process spatially correspondingvideo lines in temporally spaced video fields. For example, a videosignal processing system may process line X of Bottom Field N and line Xof Bottom Field N+1 simultaneously. Such a video signal processingsystem may, for example, add or subtract samples from the correspondinglines. In such a signal-processing scenario, it may be desirable for thesystem to synchronize the sub-carrier used to modulate information ofBottom Field N, line X and the sub-carrier used to modulate informationof Bottom Field N+1, line X. For example, the system may synchronize thesub-carriers by adjusting the phase of one or more of the video signals.

Additionally, by the time the system performs such synchronization, thesystem may, for example, only have digital samples of originally analogsignals. If the sampling period is greater than the desired sub-carriersynchronization resolution, it may be desirable for the system to havethe capability to synchronize the sampled signals with a resolution thatis smaller than the period at which the original signals were sampled(i.e., perform fractional sample synchronization).

Note that though the example illustrated in FIG. 1 relates to a typicalinterlaced video stream, and the following discussion may presentaspects of the present invention in the context of a video stream, thescope of the present invention should, by no means, be limited to videostreams or the processing thereof. For example, and without limitation,many of the various aspects of the present invention apply to the audiocontext as well as the video context.

FIG. 2 is a diagram illustrating aspects of a system 200 forsynchronizing signals according to their sub-carriers in accordance withvarious aspects of the present invention. Though the exemplary system200 is generally directed to outputting synchronized video signals, andthe system 200 will be described in the video context, the system 200 isan illustrative system. Accordingly, the scope of various aspects of thepresent invention is, by no means, to be limited to video apparatus andmethods.

In the exemplary system 200, incoming video arrives on the video inputline 205. The sync processor 210 receives incoming video on the videoinput line 205 and processes the incoming video. The sync processor 210may, for example, process information from an incoming sampled videosignal to determine indications of horizontal and vertical sync. Thesync processor 210 may utilize phase lock loop circuitry to produce andoutput horizontal and vertical sync signals. The sync processor 210 mayoutput a horizontal sync signal near the beginning of each incoming lineof video information. Similarly, the sync processor 210 may output avertical sync signal near the beginning of each incoming field or frameof video information. Various system components may receive thehorizontal and vertical sync signals and use the horizontal and verticalsync signals for timing synchronous signal processing activities.

The sync processor 210 may also determine a field identifier forincoming video information and output the field ID signal to varioussystem components. Such a field identifier may, for example, include asequence number or an indication of polarity of a received video field,such as a “top field” and “bottom field” indication. The sync processor210 may also determine other signals from the incoming video to be usedby the system 200 for synchronization and other timing-based decisions.

Various aspects of the illustrated exemplary synchronization system 200are generally directed to synchronizing adjacent video lines in the samevideo field using line buffering. Such aspects and components may be,for example, enclosed in dashed block 215. The following discussion willgenerally focus on other aspects of the exemplary synchronization system200, addressing components in the dashed block 215 when necessary. Forexample, line buffer 220 receives an incoming sampled signal carrying aline of video information and delays outputting the sampled signal forapproximately one line period. The line buffer 220 outputs the delayedsampled signal on line A. In the following discussion, the sampledsignal output from the line buffer 220 on line A will be referred to asthe “current sampled signal.”

The field capture module 225 receives the current sampled signal fromthe line buffer 220. The field capture module 225 may also receive avariety of signals from the sync processor 210. Such signals mayinclude, for example, a horizontal sync signal, a vertical sync signaland an indication of polarity of the video field corresponding to thecurrent sampled signal. The field capture module 225 generally capturessampled signal information into memory.

The field capture module 225 may, for example, crop unwanted informationfrom the current sampled signal, thereby conserving memory resources.The field capture module 225 may determine the field polarity of thecurrent video field of which the current sampled signal is a part. Thefield capture module 225 may determine which lines of the current videofield carry active video information and which samples of those linescarry active video information. Such information may, for example, bepredetermined and stored in registers. Alternatively, such informationmay be variable and responsive to real-time conditions.

For example, FIG. 3 shows a diagram 300 illustrating aspects of storedvideo signal samples and additional information in accordance withvarious aspects of the present invention. The diagram shows an exemplaryline of video 310, which may include data and synchronizationinformation in a blanking portion 320 and active video data in an activevideo portion 330. The diagram 300 also shows an exemplary storedportion 340 of video information that may correspond to stored portionsof the exemplary line of video 310. The exemplary stored portion 340may, for example, include an active video information portion 350,corresponding to the active video portion 330 of the exemplary line ofvideo 310, a sub-carrier burst portion 355, corresponding to thesub-carrier burst portion of the exemplary line of video 310, and anadditional information portion 360, which may, for example, containstored information regarding samples cropped from the exemplary line ofvideo 310.

Referring back to FIG. 2, the field capture module 225 may track theline of a video field to which the current sampled signal corresponds.For example, the field capture module 225 may count horizontal synchpulses after each vertical sync pulse to track the video line numbercorresponding to the current sampled signal. The field capture module225 may then compare the count of horizontal sync pulses to a registerto determine if the current sampled signal carries active videoinformation. The register may vary depending on the polarity of thecurrent video field. For example, in an exemplary video field, the videofield may have twenty-one lines of information prior to lines containingactive video information. The field capture module 225 may then crop (ordiscard) lines of video information, or their respective signal samples,that do not contain active video information.

Similarly, for each line of video that contains active videoinformation, the field capture module 225 may track which samples of thecurrent sampled signal contain active video information and whichsamples contain sub-carrier burst. For example, the field capture module225 may crop samples from the current sampled signal that correspond tohorizontal sync information and other non-active video information atthe beginning of the video line. For example, the field capture module225 may discard samples from the horizontal sync information to thebeginning of sub-carrier burst information. The number of samplesdiscarded at the beginning of a video line may be constant or variable,or may be predetermined or determined in real-time. For the followingdiscussion, this number of cropped samples at the beginning of the videoline will be referred to as “N1.”

After discarding the first N1 samples from the current sampled signal,the field capture module 225 may capture a group of samplescorresponding to active video information preceded by a sub-carrier syncburst. The number of samples captured may be constant or variable, ormay be predetermined or determined in real-time. For example, the numberof samples may be a number of samples corresponding to approximately55.3 microseconds of active video information preceded by a sub-carriersync burst. Depending on the sampling rate, this may, for example,correspond to approximately 1.5K samples. For the following discussion,the number of samples captured during this phase will be referred to as“N2.” The field capture module 225, during or after capturing the N2samples of the current sampled signal, may store the N2 samples in amemory 230.

The memory 230 generally stores information. The memory 230 may, forexample, include a dynamic random access memory (DRAM). The memory 230may be general or may be specially adapted for storing multiple videofields of information. The memory 230 may, for example, be adapted tostore lines of video information for a top video field and a bottomvideo field. The memory 230 may include volatile and non-volatilememory. The memory 230 may, for example, be integrated into a modulewith the field capture module 225 or may be standalone hardware. Thememory 230 may include any device that effectively stores information.

After capturing the N2 samples from the current sampled signal, thefield capture module 225 may determine the number of signal samples thatoccur before the field capture module 225 receives the next horizontalsync pulse from the sync processor 210. The field capture module 225 mayestimate this number, but it may generally be more accurate to count thesamples, particularly in a signal processing system where such number ofsamples may change. For the following discussion, this number of samplesbetween the last captured sample for a line of video information and thehorizontal sync pulse for the next line of video information will bereferred to as “N3.” The magnitude of N3 may, for example, correspond toapproximately a number of samples that occupy 1.5 microseconds. Anexemplary magnitude measured in signal samples may be, for example,forty or forty-one.

In a signal processing system where N3 may vary, the field capturemodule 225 may store the value of N3 in the memory 230. The fieldcapture module 225 may store the value of N3 in a contiguous manner withthe N2 captured samples from the current sampled signal. Alternatively,for example, the field capture module 225 may store the value of N3 inany manner that may indicate a relationship between N3 and the currentsampled signal.

The field capture module 225 may continue to capture lines of video, orportions thereof, received in sampled signals for a number of linescorresponding to the number of lines containing active video informationin the field. The number of lines may be, for example, a predeterminedand constant value or may, for example, be a variable value adjustablein real-time. For the present example, the number of lines per field isconstant, at least for a particular video field polarity being received.For example the number of lines captured in a video field may be 241.

After capturing information from the last line in a video field, thefield capture module 225 may count the number of signal samples that arenot captured from the last captured sample of the last video line of avideo field to the horizontal sync signal for the first line to becaptured in the next video field. For the following discussion, thisnumber will be referred to as “N4.” N4 may have a value of, for example,37,752. The field capture module 225 may store the value of N4 similarto the value of N3. During initialization, the first value of N4 may bezero, since a previous field has not yet been captured.

Table 1 shows an illustrative data structure that the field capturemodule 225 may form in the memory 230. The value of N4, which may be thenumber of signal samples skipped between the last sample stored from theprevious video field and the horizontal sync pulse before the firstsample captured in the next video field, may be stored with the storedsamples for the first line captured. The value of N3_(—)1, which may bethe number of signal samples skipped between the last sample of thefirst line captured and the horizontal sync pulse before the firstsample of the second line captured, may be stored with the storedsamples for the second line captured, and so on. Note, however, thatthis data structure is only exemplary and should, by no means, limit thescope of various aspects of the present invention.

TABLE 1 N4 Line 0 (first line captured) N3_1 Line 1 (second linecaptured) N3_2 Line 2 N3_3 Line 3 N3_ . . . Line . . . N3_239 Line 239N3_240 Line 240

The previously described cropping functionality is exemplary and should,by no means, limit the scope of various aspects of the present inventionto cropping functionality. For example, the field capture module 225 maynot perform cropping. Alternatively, for example, the field capturemodule 225 may generate some other signal derived from the originalsampled signal.

The field retrieve module 235 retrieves stored video information fromthe memory 230 that the field capture module 225 stored in the memory230. The field retrieve module 235 may retrieve the stored videoinformation in coarse synchronization with currently received videoinformation. For the system 200 to output and align stored videoinformation with currently received video information, the fieldretrieve module 235 may read stored video information out of memory inadvance of the need for such stored video information at the systemoutput.

The field retrieve module 235 may operate in a coarse synchronizationmode. When the system 200 is in a coarse sync mode, the field retrievemodule 235 may read, for example, the first set of samples of the firstline of video of the designated field buffer in the memory 230. Thefield retrieve module 235 may feed a number of samples to the fractionalsample delay (FSD) filter 240 in preparation for outputtingcorresponding video information in synchronization with current videoinformation output from the line buffer 220.

The field retrieve module 235 may then wait to receive a signal toproceed from the coarse sync module 245. Once the field retrieve module235 receives a signal to proceed from the coarse sync module 245, thefield retrieve module 235 may continually retrieve samples from thememory 230 and pass the retrieved samples, along with additionalsamples, to the FSD filter 240 until directed to stop by the coarse syncmodule 245.

The field retrieve module 235 may reconstruct video signals frominformation retrieved from the memory 230. In this reconstructingprocess, the field retrieve module 235 may access information used ordetermined by the field capture module 225 during the field captureprocess. For example, the field retrieve module 235 may retrieve samplesof stored active video information from the memory 230 corresponding toa first video line and output the retrieved samples. The field retrievemodule 235 may then obtain the N3 value associated with the number ofsamples that the field capture module 225 cropped between the capturedsamples of the first video line and the horizontal sync of the secondvideo line. The field retrieve module 235 may then insert N3 samplesafter the output samples for the first video line to replace the N3samples that were cropped (or deleted) by the field capture module 225.The replaced samples may be, for example, null data samples.

The field retrieve module 235 may then obtain the N1 value associatedwith the number of samples that the field capture module 225 croppedbetween the horizontal sync of the second video line and capturedsamples of the second video line. The field retrieve module 235 may theninsert N1 samples after the N3 samples just inserted to replace the N4samples that were cropped from the second video line by the fieldcapture module 225.

After retrieving, restoring and outputting the stored video samplescorresponding to a last line of a video field, the field retrieve module235 may then obtain the N4 value associated with the number of samplesthat the field capture module 225 cropped between the last capturedsample of the last captured line of the video field and the horizontalsync for the first captured line of the next field. The field retrievemodule 235 may then insert N4 samples to replace the samples cropped bythe field capture module 235. The field retrieve module 235 may theninsert N1 samples to replace the samples removed from the first capturedvideo line of the next field by the field capture module 235 between thehorizontal sync signal and the captured samples of the video line.

The field retrieve module 235 may also be responsive to a sample adjustsignal from the loop control module 250. In response to the sampleadjust signal, the field retrieve module 235 may, for example, eitheradvance or delay the transmission of the retrieved and reconstructedvideo by one sample. The loop control module 250 may utilize thiscapability of the field retrieve module 235 to adjust thesynchronization (or timing) between the current and retrieved video by afull sample. For example, by inserting a null sample in the retrievedand reconstructed video, the field retrieve module 235 may delay thetiming of the retrieved video information by one sample relative to thecurrent video, and the field retrieve module 235 may advance the timingof the retrieved and reconstructed video by one sample relative to thecurrent video by deleting a sample from the retrieved video.

The loop control module 250, which will be discussed in more detaillater, controls the FSD filter 240 by fractional samples. When the loopcontrol module 250 adjusts the delay of the FSD filter 240, and thatadjustment creates a carry-out from the fractional portion of the sampletiming, that carry-out may trigger the loop control module 250 to outputa sample adjust signal to the video retrieve module 235 to effect awhole-sample timing adjustment.

The loop control module 250 may be configured to modify the fractionalsample delay from the FSD filter 240 and the full sample delay from thefield retrieve module 235 near, for example, the end of a video line.Thus, the field retrieve module 235 may receive the video adjust signalwhen the field retrieve module 235 is adding null samples to theretrieved video information. The field retrieve module 235 may thenadjust the number of samples inserted before or after the retrievedvideo line that the field retrieve module 235 is presentlyreconstructing.

The coarse sync module 245 generally determines the sync lock status ofthe system. The coarse sync module 245 may determine, for example, whenthe system 200 is in an unlocked state, waiting to acquire coarsesynchronization, or in a coarse locked state. The coarse sync module 245may also monitor the coarse synchronization status during operation todetermine if synchronization problems arise.

The synchronization status of the system 200 is unlocked, for example,when the system is initialized. The system 200 may enter an unlockedstate during operation for various reasons, for example, the arrival ofparticular non-standard video signals. When in the unlocked state, thecoarse sync module 245 may direct the FSD filter 240 not to adjust thetiming (or phase) of the retrieved video signal from the field retrievemodule 235. The FSD filter 240 may then remain in this no-time-shiftstate until directed to resume time-shifting operation by the coarsesync module 245. In other words, the coarse sync module 245 mayeffectively shut down fine sync operation when the coarse sync module245 determines that coarse synchronization does not exist.

The coarse sync module 245 may synchronize the system according to thehorizontal sync signal from the sync processor 210. For example, whenincoming video arrives at the video input line 205, the sync processor210 may signal the field capture module 225 and the course sync module245 when the sync processor determines that it has obtained valid sync.Valid sync may include, for example, a reliable lock on horizontal sync,vertical sync and field ID of the incoming video. The field capturemodule 225 may then, for example, capture the next two video fieldsarriving to fill the top and bottom field buffers in the memory 230.Note that the two-video-field capture is merely exemplary, andaccordingly, the scope of various aspects of the present inventionshould, by no means, be limited to two fields or to video information ingeneral. The coarse sync module 245 may wait for the field capturemodule 225 to accomplish this field buffer loading.

Near the end of capturing two consecutive fields in the memory 230, thecoarse sync module 245 may direct the field retrieve module 235 to readthe start of the field buffer with the field polarity matching the nextexpected arriving field of video. The field retrieve module 235 may, forexample, read the first set of video samples for the appropriate storedfield and wait for the coarse sync module 245 to signal the fieldretrieve module 235 to proceed. The coarse sync module 245 may thenmonitor the signals from the sync processor 210 to determine when thecurrently arriving video is at a sample point matching that of thecorresponding first stored sample. For example, the coarse sync module245 may count horizontal sync signals from the sync processor 210 todetermine when the current arriving video corresponds to the firststored line of video. Then the coarse sync module 245 may count to thesample of the current video line that matches the first stored sample.

For example, the N+1th sample of the current video line may follow thehorizontal sync of the current video line by N1 samples. The firstsample of a line of stored video may be the N1+1th sample of that lineand may follow the horizontal sync signal of the stored video line by N1samples. Therefore, starting the stored video on the N1+1th sample atthe same time as the N1+1th sample of current video may result in thestored video being synchronized with the current video to the nearestclock cycle, with reference to the horizontal sync signal.

Once coarse synchronization lock has been achieved, the coarse syncmodule 245 may direct the components of the fine synchronization loop,including the loop control module 250, to begin fine sync operation.During operation of the fine synchronization loop, the coarse syncmodule 245 may, for example, continually compare the N1+1th samples ofthe current and stored video for each active line of video. The coarsesync module 245 may, for example, contain a register that determines howmany sample times of difference are allowed before the coarse syncmodule 245 declares an out of sync condition. Upon declaring an out ofsync condition, the coarse sync module 245 may disable the fine syncloop and notify other system components that depend on synchronizationof the out-of-sync condition.

The fractional sample delay (FSD) filter 240 operates to delay a sampledinput signal by a fraction (typically a binary fraction) of the samplinginterval of the sampled input signal. For example, the FSD filter 240may delay the sampled input signal by steps of 1/32 of the sampleinterval of the input signal. The FSD filter 240 may, for example,utilize a poly-phase filter as a delay element. The loop control module250 may indicate to the FSD filter 240 the number of fractional samplesto delay the sampled input signal. The FSD filter 240 may then outputthe fractional phase shifted stored video signal on line G.

The FSD filter 240 may utilize a filter having a particular number oftaps. During acquisition of coarse lock, as discussed previously, thefield retrieve module 235 may forward a number of samples to the FSDfilter 240 to prepare the FSD filter 240 to output the retrieved sampledsignal upon command (i.e., to “prime” the FSD filter 240). This numberof samples may depend, for example, on the number of taps used in theFSD filter 240 and on other aspects of the FSD filter 240 configuration.

The burst phase detector 255 receives the current video output from theline buffer 220 on line A and receives the stored video output from theFSD filter 240 on line G. The burst phase detector 255 may analyze thesub-carrier bursts from the two input signals and measure the differencein phase between the sub-carrier bursts. The burst phase detector 255may then output this difference to the loop control module 250. Aspectsof the burst phase detector 255 will be discussed in more detail in thediscussion of FIG. 4.

The loop control module 250 performs synchronization between the currentand stored video signals. The loop control module 250 generally performssub-carrier burst synchronization that may be considered finesynchronization relative to the horizontal sync-based synchronizationcoordinated by the coarse sync module 245. The loop control module 250,generally in conjunction with the phase detector and the FSD filter 240,effectively implement a phase lock loop. The reference input may be thesub-carrier burst from the current sampled signal, the feedback inputmay be the sub-carrier burst from the stored sampled signal, and thecontrol variable may be the delay of the stored sampled signal output,as implemented in fractional samples by the FSD filter 240 and wholesamples by the field retrieve module 235. The loop control module 250may, for example, be constrained to adjust its delay control outputafter the end of an active video line (e.g., during the horizontalblanking interval). Aspects of the loop control module 250 and the burstphase detector 255 will now be discussed in more detail with regard toFIG. 4.

FIG. 4 is a diagram illustrating exemplary portions of a synchronizationcontrol loop 400 in accordance with various aspects of the presentinvention. Current and stored sampled video signals may be input torespective band-pass filters 410-411. The band-pass filters 410-411 may,for example, remove DC components of the sampled video signals. Thestored sampled video signal output from its respective band-pass filter411 may be input to a 90-degree phase shifter 421. The 90-degree phaseshifter 421 may, for example, be implemented using a Hilbert filter. The90-degree phase shifter 421 may have, for example, an inherent sampledelay. Accordingly, to maintain synchronization between the current andstored sampled video signals, the current sampled signal output from itsrespective band-pass filter 410 may be input to a delay element 420.

The output signals from the 90-degree phase shifter 421 and the delayelement 420 may be input to a phase detector circuit 430. The phasedetector circuit 430 may multiply corresponding sync burst samples fromthe delayed current sampled signal and the phase-shifted and delayedstored signal. The phase detector circuit 430 may then output a seriesof samples during the burst, which represent the phase differencebetween the burst samples.

Since the phase detector circuit 430 phase difference output may containhigher frequency components, such as a frequency component at twice thesub-carrier frequency, the output of the phase detector circuit 430 maybe filtered using a band-stop filter 440 to remove such undesirablefrequency components.

The output of the band-stop filter 440 may be coupled to the input of anintegrator 450. The integrator 450 may, for example, include anaccumulator 452 that keeps a running sum of the filtered output samplesfrom the phase detector 430 during sync bursts. For example, everysample during a burst, the phase detector 430 may output a product ofits input samples as an indication of phase difference. Accordingly, theaccumulator 452 may sum these phase difference indications for theduration of the sync burst. The accumulator 452, or integrator 450, may,for example, be configured to perform the accumulation, or integration,only when the input to the phase detector circuit 430 includes samplesof the sub-carrier bursts.

The accumulator 452 may output the accumulated sum of the phasedifference indications to a bit selector 460 that selects the bits fromthe accumulator 452 output on which to base a fractional sample phaseshift decision. The bit position of the selected bits may generallydetermine the gain of the phase control loop. The selected bits from thebit selector 460 may also be rounded 470 to arrive at an appropriatephase shift command. An overflow in the accumulator 452 may, forexample, be used by the loop control module 250, as mentioned earlier,to signal the field retrieve module 235 to effect a full-sample phaseshift to the retrieved video signal. Such a phase-shift signal may beoutput to the field retrieve module 235, for example, on line 480. Thefractional sample phase shift command may then be output to the FSDfilter 240 on line 490.

Various aspects of the systems shown in FIGS. 2 and 4 may be implementedin a variety of hardware and software implementations. For example, thetime-sensitive or processing-intensive modules may be performed inintegrated hardware modules, while various other aspects may beimplemented using a processor executing software or firmwareinstructions. Accordingly, the scope of various aspects of the presentinvention should, by no means, be limited to particular hardware orsoftware configurations.

FIG. 5 is a diagram illustrating aspects of an exemplary method 500 forsynchronizing video signals according to their sub-carriers inaccordance with various aspects of the present invention. The method 500includes receiving a current sampled video signal 510, for example. Themethod 500 may generate synchronization signals 520, for example, ahorizontal sync signal, a vertical sync signal, and a video framepolarity indication. Such synchronization signals may be utilized byvarious other method and system aspects for timing and synchronization.

The method 500 may include cropping the current sampled signal 530 toremove samples representing information for which storage isunnecessary. For example, the cropping step 530 may include croppingdata information contained in horizontal and vertical blanking intervalsand may include cropping portions of video synchronizing information.The cropping step 530 may, for example, crop information in a line ofvideo information between a horizontal sync signal for the line of videoinformation and sub-carrier burst information for the line of videoinformation. The cropping step 530 may also include, for example,cropping information following active video information in a line ofvideo information.

The previously described cropping step is exemplary and should, by nomeans, limit the scope of various aspects of the present invention tocropping functionality. For example, the method 500 may skip thecropping step 530, choosing to present the original sampled signal tothe following storing step 540. Alternatively, for example, the method500 may include an alternative step to the cropping step 530 thatgenerates some other signal derived from the original sampled signal.

The method 500 may further include storing the cropped current sampledsignal in memory 540. The storing step 540 may include storinginformation indicating which samples were cropped from the currentsampled signal. Such information may be utilized later, for example, inreconstructing the stored signal after portions of the stored signal areread out from memory. The method 500 may include storing a plurality ofvideo fields of video lines 540. The storing step 540 may include, forexample, storing an entire prior frame of video lines prior to thecurrent video line.

In addition to storing portions of the current sampled signal, themethod 500 may also output the current sampled signal and a sampledsignal retrieved from memory in a phase-synchronized fashion. The method500 may include reading a stored sampled signal from memory 550 thatcorresponds to the current sampled signal. For example, the storedsampled signal may correspond to the current sampled signal in theprevious video frame. For example, the current sampled signal may becarrying video information from line 50 of video frame N, and the storedsampled signal may be carrying video information from line 50 of videoframe N−1.

The method 500 may then restore the stored sampled signal 555 to atleast the approximate length of the stored sampled signal prior tocropping. For example, the cropping step 530 may have removed the firstN samples of the stored sampled signal prior to storage. The restoringstep 555 may then restore the N samples of the stored sampled signal byinserting null data samples in place of the N cropped samples. Therestoring step 555 may obtain an indication of N from a register, ormay, for example, read the value of N from memory when reading thecorresponding stored sampled signal from memory.

The method 500 may then output the restored sampled signal 560 coarselysynchronized with the current sampled signal. For example, theoutputting step 560 may include utilizing synchronization signalsgenerated in the sync signal-generating step 520. For example, theoutputting step 560 may include timing the output of the restoredsampled signal based on a horizontal sync signal and vertical syncsignal obtained from the current sampled signal.

The method 500 may then determine a fine phase (or timing) adjustment570 for synchronizing the output current sampled signal and the outputrestored sampled signal. The fine phase (or timing)adjustment-determining step 570 may include, for example, determining aphase (or timing) difference between the output current sampled signaland output restored sampled signal by measuring phase difference betweentheir respective sync burst signals. The fine phaseadjustment-determining step 570 may, for example, utilize components andmethods discussed previously with regard to the systems illustrated anddescribed in FIGS. 2 and 4. The fine phase adjustment determining step570 may include determining a fine phase adjustment by calculating aninteger number of fractional sample intervals that correspond mostclosely to the desired phase adjustment.

The method 500 may then include adjusting the phase (or timing) 580 ofthe restored sampled signal according to the determined fine phase (ortiming) adjustment. The fine phase adjusting step 580 may include, forexample, utilizing a fractional sample delay filter, which may include apoly-phase filter, to adjust the timing of the output restored sampledsignal by a fraction (typically a binary fraction) of the samplinginterval of the sampled signal. The fine phase adjusting step 580 mayalso include adjusting the phase of the output restored sampled signalby whole samples by inserting or deleting whole samples from the outputrestored sampled signal.

The method 500 may continue receiving, cropping, storing and outputtingcurrent sampled signal signals. The method 500 may also continuereading, restoring, outputting and synchronizing stored sampled signalsignals corresponding to the current sampled signal.

The method 500 was described in the context of video signals. However,the scope of various aspects of the present invention should, by nomeans, be limited to video systems and methods. For example, variousaspects of the present invention may be utilized for any system thatoutputs synchronized signals. Such a system may include, for example, asystem that processes time-shifted audio signals.

The previous discussion generally focused on outputting a pair ofsynchronized signals. However, in no way, should the scope of variousaspects of the present invention be limited to systems and methods forgenerating only a pair of synchronized signals. Various aspects of thepresent invention are readily extendible to outputting any plurality ofsynchronized signals or groups of synchronized signals.

In summary, various aspects of the present invention provide a systemand method for synchronizing signals in a signal processing system.While the invention has been described with reference to certain aspectsand embodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the invention without departing from its scope.Therefore, it is intended that the invention not be limited to theparticular embodiment disclosed, but that the invention will include allembodiments falling within the scope of the appended claims.

1. A method for synchronizing sampled signals, the method comprising:using one or more circuits to perform the steps of: receiving a firstsampled signal; generating a signal comprising a portion of the firstsampled signal; storing the generated signal in a memory; receiving asecond sampled signal; reading the generated signal from the memory;generating a restored sampled signal using the generated signal;outputting the second sampled signal; and outputting the restoredsampled signal synchronized to the second sampled signal.
 2. The methodof claim 1, further comprising storing in the memory an indication of aportion of the first sampled signal not used in the generated signal. 3.The method of claim 2, wherein said generating a restored sampled signalcomprises reading from the memory the indication of the portion of thefirst sampled signal not used and adding samples to the generated signalread from the memory according to the indication of the portion of thefirst sampled signal not used.
 4. The method of claim 1, wherein thefirst sampled signal carries video information, and said generating thesignal comprising the portion of the first sampled signal comprisesremoving at least a portion of samples from the first sampled signalthat correspond to non-active video information.
 5. A method forsynchronizing sampled signals, the method comprising: using one or morecircuits to perform the steps of: receiving a sampled signal; retrievinga stored sampled signal from a memory; generating a coarsesynchronization signal; outputting the sampled signal; outputting thestored sampled signal in response to the coarse synchronization signal;determining a phase difference between the output sampled signal and theoutput stored sampled signal; determining a phase adjustment based onthe phase difference between the output sampled signal and the outputstored sampled signal; and adjusting the phase of at least one of theoutput sampled signal and the output stored sampled signal according tothe determined phase adjustment.
 6. The method of claim 5, wherein saiddetermining a phase adjustment comprises determining the phaseadjustment by converting the phase difference to at least one of anumber of samples and a number of fractional samples.
 7. The method ofclaim 6, wherein said adjusting the phase comprises time shifting theoutput stored sampled signal by at least one of the number of samplesand the number of fractional samples.
 8. The method of claim 5, furthercomprising monitoring coarse synchronization between the output sampledsignal and the output stored sampled signal by comparing arrival timesof predetermined corresponding samples in the output sampled signal andthe output stored sampled signal.
 9. The method of claim 8, wherein thearrival times are measured relative to the generated coarsesynchronization signal.
 10. The method of claim 5, wherein saidgenerating a coarse synchronization signal comprises generating thecoarse synchronization signal using a phase lock loop locked tohorizontal sync signals in a stream of sampled signals carryingrespective video line information.
 11. A system for synchronizing afirst sampled signal and a second sampled signal, the system comprising:one or more circuits that receives the first sampled signal andgenerates a synchronization signal based on at least one of the firstsampled signal and a sampled signal preceding the first sampled signal;said one or more circuits retrieves a stored sampled signal from amemory and generates the second sampled signal based on the storedsampled signal; said one or more circuits receives the synchronizationsignal and the second sampled signal and outputs the second sampledsignal synchronized to the first sampled signal in response to thesynchronization signal; and said one or more circuits receives the firstsampled signal and receives the second sampled signal output andgenerates an indication of phase difference between the first sampledsignal and the second sampled signal.
 12. The system of claim 11,wherein said one or more circuits comprises a sub-circuit that receivesthe indication of phase difference and the second sampled signal andadjusts output timing of the second sampled signal based on theindication of phase difference.
 13. The system of claim 12, wherein thesub-circuit comprises a fractional sample delay filter.
 14. The systemof claim 11, wherein said one or more circuits comprises a sub-circuitthat determines the phase difference between the first and secondsampled signals by analyzing sub-carrier burst signals in each of thefirst and second sampled signals.
 15. The system of claim 11, whereinthe indication of phase difference comprises an integer number offractional samples.
 16. A system for synchronizing a first sampledsignal and a second sampled signal, the system comprising: a first logiccircuit that comprises a memory; a second logic circuit that receivesthe first sampled signal and generates a signal comprising a portion ofthe first sampled signal; a third logic circuit coupled to the first andsecond logic circuits that receives the generated signal from the secondlogic circuit and stores the generated signal in the first logiccircuit; a fourth logic circuit coupled to the first logic circuit thatretrieves the generated signal stored in the first logic circuit andgenerates a restored sampled signal using the generated signal; a fifthlogic circuit coupled to the fourth logic circuit that receives therestored sampled signal from the fourth logic circuit and outputs therestored sampled signal synchronized with the second sampled signal. 17.The system of claim 16, wherein a portion of the first sampled signalnot used by the second logic circuit to generate the generated signalcorresponds to non-active video information.
 18. The system of claim 16,wherein the second logic circuit outputs an indication of a portion ofthe first sampled signal not used by the second logic circuit togenerate the generated signal and the third logic circuit stores theindication of the portion of the first sampled signal not used in thefirst logic circuit.
 19. The system of claim 18, wherein the fourthlogic circuit further retrieves from the first logic circuit theindication of the portion of the first sampled signal not used and addssamples to the generated signal according to the indication of theportion of the first sampled signal not used.
 20. The system of claim16, further comprising a sixth logic circuit coupled to the fifth logiccircuit that receives the second sampled signal and generates asynchronization signal based on the second sampled signal, and whereinthe fifth logic circuit receives the synchronization signal from thesixth logic circuit and outputs the restored sampled signal in responseto the synchronization signal.
 21. A method for synchronizing sampledsignals, the method comprising: using one or more circuits to performthe steps of: receiving a first sampled signal; storing a stored sampledsignal in a memory, the stored sampled signal comprising a portion ofthe first sampled signal; receiving a second sampled signal; reading thestored sampled signal from the memory; generating a restored sampledsignal based on the stored sampled signal read from the memory;outputting the second sampled signal; and outputting an output sampledsignal synchronized to the second sampled signal, the output sampledsignal being based on the restored sampled signal.
 22. The method ofclaim 21, wherein the first sampled signal comprises sub-carrier burstsamples, and wherein outputting the output sampled signal synchronizedto the second sampled signal comprises utilizing the sub-carrier burstsamples to synchronize the output sampled signal to the second sampledsignal.
 23. The method of claim 21, wherein outputting the outputsampled signal synchronized to the second sampled signal comprises:initially outputting the output sampled signal synchronized to thesecond sampled signal using open loop timing control; and thereafteradjusting the timing of the output sampled signal relative to the secondsampled signal using closed loop timing control.
 24. A system forsynchronizing a first sampled signal and a second sampled signal, thesystem comprising: one or more circuits that receives the first sampledsignal and the second sampled signal; a memory circuit communicativelycoupled to said one or more circuits; said one or more circuits stores astored sampled signal in the memory circuit, the stored sampled signalcomprising at least one of the first sampled signal and a signal derivedfrom the first sampled signal; said one or more circuits reads thestored sampled signal from the memory circuit; said one or more circuitsoutputs the second sampled signal; and said one or more circuits outputsan output sampled signal synchronized to the second sampled signal, theoutput sampled signal being based on the stored sampled signal read fromthe memory circuit.
 25. The system of claim 24, wherein the firstsampled signal comprises sub-carrier burst samples, and wherein said oneor more circuits outputs the output signal synchronized to the secondsampled signal utilizing the sub-carrier burst samples to synchronizethe output signal to the second sampled signal.
 26. The system of claim24, wherein the signal derived from the first sampled signal comprises acropped version of the first sampled signal.
 27. The system of claim 24,wherein said one or more circuits comprises: one or more sub-circuitsthat outputs the output sampled signal synchronized to the secondsampled signal using open loop timing control; and said one or moresub-circuits adjusts the timing of the output sampled signal relative tothe second sampled signal using closed loop timing control.